1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which is used in a semiconductor manufacturing process, and more particularly, to a method of manufacturing a semiconductor device by which the CDs of patterns of minute grooves (trenches) and holes (vias) can be formed with high accuracy when a multi-layer wiring pattern below a predetermined resolution limit is formed using a dual damascene method.
2. Description of the Related Art
As semiconductor devices have become more highly integrated, wirings or separation widths required in a manufacturing process thereof have also become minute. In general, minute patterns are formed by forming a resist pattern using a photolithography process and etching various layers on a base layer using the resist pattern as an etching mask. Accordingly, although the photolithography process is important in terms of forming minute patterns, currently, even more minute patterns below a resolution limit of the photolithography process are required in the case of many semiconductor devices. Also, it is known that the resolution of an ArF liquid immersion exposure technique, which is currently performed in mainstream, has reached the limit in the 4×nm generation. Accordingly, a double patterning (DP) technique for achieving the smaller 3×nm generation has been currently vigorously developed.
Techniques of forming such patterns below a predetermined resolution limit are disclosed, for example, in Reference 1.
Reference 1 discloses a method in which a plurality of first photosensitive layer patterns, hereinafter referred to as first resist patterns, are formed, the first resist patterns are then baked, and an oxide layer is formed on the first resist patterns. Then, a plurality of second photosensitive layer patterns, hereinafter referred to as second resist patterns, are formed between the first resist patterns, and a thin layer of the base layer is etched using the first resist patterns and the second resist patterns as etching masks to form minute patterns. Such method is referred to as a lithography lithography etching (LLE) process.
According to Reference 1, minute patterns are formed using two exposure masks, and thus the minute patterns can be formed to have a line width that is smaller by half or more than that of minute patterns formed using one exposure mask. Thus, minute patterns can be formed below a predetermined resolution limit.
Meanwhile, as the semiconductor devices have become highly integrated, wirings between semiconductor devices have also become minute. In this case, however, a large capacity is generated between the wirings and thus a signal transmission speed is decreased, thereby causing delay in the operational speed. To address this problem, recently, an insulation material (low-k material) having a low relative permittivity is used as an interlayer insulation layer, and copper (Cu), which is low-resistive and has excellent resistance to electromigration, has been used as a wiring material. Also, a dual damascene method has been widely used for forming groove wirings or contact holes formed of copper.
Multi-layer Cu wirings are formed in the dual damascene method by forming an etching stop layer on a lower Cu wiring, forming a low-k layer thereon as an interlayer insulation layer, and sequentially forming a metal hard mask layer, a bottom anti-reflection coating (BARC), and a photoresist layer on the low-k layer. Then, the low-k layer is etched to form a via, a trench is etched, and then the etching stop layer is etched to connect the via, thereby additionally forming a buried Cu wiring layer.
A technique of forming multi-layer Cu wirings by using the dual damascene method is disclosed in Reference 2.
Reference 1: Japanese Patent No. 2757983; and
Reference 2: Japanese Laid-Open Patent Publication No. 2007-335450.
When patterns of multi-layer Cu wirings are formed by making patterns such as grooves (trench) and holes (via) below a predetermined resolution limit using a dual damascene method, the following problems occur.
In order to form minute patterns such as holes (vias) and grooves (trenches) below a predetermined resolution limit, a photolithography process using masks corresponding to each pattern, that is, the holes (vias) and grooves (trenches), needs to be performed. However, due to the limit of the exposure technique, in other words, due to a predetermined resolution limit, it is not possible to form pitches of 90 nm or smaller.
Also, a conventional lithography lithography etching (LLE) process includes forming a resist pattern twice using a photolithography process. In this case, when forming a second resist pattern, the shape of a first resist pattern is maintained and the second resist pattern is formed between the first resist patterns. Thus, the LLE process can be applied for forming a gate layer of a field effect transistor (FET) which has convex patterns. On the other hand, when forming concave patterns such as holes (vias) and grooves (trenches), it is necessary to form opening portions of the second resist pattern on the first resist pattern. Thus, the shape of the first resist pattern cannot be maintained when the second resist pattern are formed. Accordingly, the conventional LLE process cannot be applied in the dual damascene method of forming holes (vias) and grooves (trenches).
Also, when the dual damascene method is performed using a single hard mask layer, etching of one of the grooves (trenches) and the holes (vias) needs to be necessarily conducted using a resist pattern as an etching mask. When a resist pattern is used as an etching mask, most likely, the shape of the resist pattern changes because the etching rate of the low-k layer to a resist layer (selectivity) is not high. Since the resist layer is also etched when the low-k layer is etched, the shape of the resist pattern may be easily deteriorated. As a result, when minute patterns are formed, the transfer accuracy of the shapes of resist patterns transferred onto the low-k layer cannot be guaranteed.
Also, when the dual damascene method is performed using a photoresist as an etching mask and a via-first method, in which a hole (via) is first formed in a layer to be etched and then a groove (trench) is formed, deterioration of characteristics and shape is generated as the low-k layer is exposed to O2 plasma in an ashing process to remove the photoresist. In particular, due to the shape deterioration, a critical dimension (CD) of patterns is not within a desired dimensional range.